Present-day computer systems generally use a plurality of resources such as a central processing module, an input/output module, a main memory module and sometimes other functional modules. Quite often there is a interconnecting communication system designated as a system bus which becomes a shared resource used for transferring data between the various resource modules.
Since the system bus is only a single shared resource among various resource modules, then there is a question of access to uses of the system bus among the various competing devices. It is necessary that no one particular resource module monopolize the system bus and that there must be some system of fair allocation for bus usage among the various resource modules so that no one particular resource module is starved out of usage of the system bus.
As a result, certain types of arbitration systems or arbitration circuitry have been developed in order to allocate bus usage among the competing resource modules. Some systems use a straight priority scheme wherein the various resource, modules are given priority levels which gives them priority of access to the system bus.
There are other types of arbitration schemes such as a "round-robin" scheme in which all of the requestors or resource modules are given the same priority level but alternated in sequence for access to the bus.
The presently described arbitration logic system provides logic that can choose among three basic resource modules or requestors as to which one will be provided the use of a shared system bus at any given point in time. This arbitration logic operates to prevent any deadlock conditions or starvation conditions which would deny access to one or more of the resource modules.
Arbitration systems are also closely linked to certain types of problems which occur such as "deadlock" problems where two requesting modules can cause each other to get into a state or condition where neither of the modules can finish its operating task. Other situations occur designated as "starvation" of a resource module, where the particular resource module cannot finish its operative task clue to conditions that occur in the system.
The presently described system functions to insure equitable arrangements for bus access among competing resource modules requesting access time to use a commonly-shared bus.